IBM's Sub-1nm Chip Design Packs Nearly 100 Billion Transistors
IBM has introduced a novel chip design that could allow manufacturers to integrate 100 billion transistors onto a silicon chip roughly the size of a fingernail.
The prevailing industry standard for chip size is measured in nanometres (nm), where one nanometre equals one billionth of a metre—approximately the size of a few atoms. Currently, chips are produced at around two nanometres.
IBM asserts that its new chip technology achieves an equivalent scale of approximately 0.7nm, potentially making it the world's first chip technology below 1nm. Despite this advancement, the company notes that it will take several years before this technology is ready for mass production.
In testing, IBM's prototype demonstrated a 50% performance improvement over its existing 2nm chip, along with a 70% increase in energy efficiency.
IBM had reported similar performance and energy efficiency gains when it introduced its 2nm chip technology in 2021, with tests showing comparable leaps at that slightly larger scale.
Jay Gambetta, director of IBM Research and IBM Fellow, described the NanoStack technology as a "landmark moment" for the future of chip development.
"With our new NanoStack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," he said.
Packing-in Power
Transistors serve as the fundamental components of silicon chips, which provide computing power for a wide array of electronic devices including smartphones, gaming consoles, and laptops.
They are also essential for the high-performance computers located in data centers, which handle numerous daily digital activities such as streaming, online banking, and powering the surge in generative artificial intelligence applications.
The ability to incorporate more transistors onto a chip directly correlates with increased chip power, enabling devices to perform more complex tasks. Concurrently, chip designers aim to reduce the physical size of chips.
For decades, the number of transistors on a chip has doubled approximately every two years, a trend known as Moore's Law.
However, as chips now contain billions of transistors, sustaining this rate of growth has become increasingly challenging, and experts generally agree that this pace cannot continue indefinitely.
To extend Moore's Law, chip designers have shifted focus from solely increasing transistor density horizontally to exploring three-dimensional (3D) alternatives, effectively altering transistor shapes to increase their height.
IBM's approach involves layering sheets of transistors vertically.
Professor Alan Woodward, a computer scientist at Surrey University, likened this to constructing a large block of flats rather than individual houses in a city.
"IBM's NanoStack is like proposing a 100-story skyscraper," he said, adding that, in his view, the firm's closest competitors such as Samsung and Intel are developing 3D chip architectures closer to 30-50 stories tall.
Designing 3D chips presents challenges including heat management, as transistors generate heat during operation and heat naturally rises.
Additionally, when the layers separating transistors are too thin, it can prevent them from switching off properly, which can impair chip functionality.
"I think it's fair to say IBM's proposals are the most ambitious," said Prof Woodward.
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